Mask design outlined

You will be creating a set of cells /structures, which will be combined in a number of different ways to create the design you want; the process can be best illustrated by a simple example: Say that you have two different devices, A and B, that you wish to fabricate on one wafer, and three different variations of each device: A1, A2, A3, and B1, B2, B3.

You will create structures for each device, and a top-level (master) structure, WAFER, which will show how all the designs are laid out over the entire silicon wafer (the names are only used here as examples, and may be changed at will). You wish to have bonding pads, for electrical connections, exactly the same on all devices for simplicity in testing. You would therefore create a structure called PADS with bonding pads on the metal layer of the mask and "via" holes through the top insulation / passivation layer of the mask (if you have one) so that it will be possible to make connections to the bonding pads.

As an aside, you want bonding pads to be several hundred microns each side to make it easy to connect wires to them. Your foundry may specify fixed sizes and positions for bonding pads.

You will then create structures A and B - which will contain everything common to designs A1, A2, A3, and B1, B2, B3, respectively. You will place an "instance" of the structure PADS in structure A, and one in structure B. Your software will display PADS as either a box with a label, or an actual picture of the bonding pads / vias that you laid out. In order to see where you're going when wiring them to other parts of your design, you will have to make sure that your software displays them in the latter manner.

You will now create structure A (and B), to contain all the common features that you need for A1..A3 (and B1..B3). When working in structure A (or B), you will not be able to alter PADS unless you "push down" into it. You will then be able to alter PADS, but remember that the alterations will also be reflected in structure B, which you will not see while working on structure A. As the design grows, this gets more and more complicated, so you need to be reasonably organised to keep track of it.

Now you create structures A1 to A3, each containing an instance of A, and the same for B. You can now push down from A1 to A, then to PADS, if you wish. Make the necessary additions to each of the designs, and now you are ready to lay them out on WAFER.

Draw a big circle on an unused layer on WAFER to illustrate the area of the silicon wafer on which the design is to be fabricated. Place instances of your structures (A1..A3, B1..B3) within this circle. Remember that your wafer will have flats ground into it to indicate the orientation of crystal planes, and also that it will be handled at the edges, so try not to put structures too close to the edge (leave gap of 5mm or so). An option that may help you with this task is the "array" option, which puts down a repeat of one structure design across a specified area. This is useful, but an array of structures is usually treated as a single object, so once an array of A1s has been created you cannot delete one and replace it with a B3; you have to delete the entire array and re-do the design with a B3 in the desired position.

Alignment marks. In order to line one layer up with a previously fabricated layer, when performing photolithography, it is necessary to incorporate appropriate marks into your mask design to facilitate this. The foundry producing the devices will probably have specific marks that they would like you to use, and these may need to be placed in a specific position on your design. They may also have additional requirements; such as the inclusion of a scribe lane around each chip, to indicate where the wafer is to be cut when it is diced, the inclusion of a unique mask number, and an indication of layer names on the mask so that it is possible to tell by looking how far through the fabrication process a wafer has progressed. See figure 19.

Figure 19.